Design Engineering Architect — Memory Modeling Portfolio

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Overview:

This role sits at the intersection of deep protocol expertise and direct partnership with our customers. As a Design Engineering Architect embedded within Cadence’s Memory Model Portfolio (MMP) R&D team, you will be the primary Korea-based expert for the UFS/Unipro/MPHY/RMMI protocol stack—on the ground with customers, inside their verification challenges, and trusted by the global MMP team to craft solutions as well as to raise the collective expertise of the engineers around you.

You will work with leading electronics companies across hyperscale and AI computing, mobile, automotive, and defense/aerospace—helping them deploy, debug, and integrate complex memory protocol IP on our industry-leading Palladium and Protium hardware emulation platforms. This is not a background support role. You are a go-to expert who can fluently read a room, debug...