Lead DRAM Layout Design Engineer — Mixed-Signal Focus

3050 Micron Semiconductor Mexico, S.de R.L. de C.V. is seeking a skilled layout engineer in Mexico, Jalisco. The role involves layout implementation, dissecting designs at the chip level, and developing methodologies for advanced DRAM products.

The ideal candidate must have over 5 years of experience in layout design, a BS/MS in Electrical or Computer Engineering, and proficiency in Cadence Virtuoso Suite. Strong problem-solving skills and effective communication are essential for collaboration with global teams.