Full-time
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Principal DDR Verification Engineer
Posted by Cadence System Design and Analysis • June 07, 2026
Description
- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
- 4+ years of Design Verification experience with SV/UVM
- Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
- Design Verification experience verifying complex designs and leading projects from concept to verification closure.
- Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
- Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
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